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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICM_TYPER, Distributor MSI Type Register</h1><p>The GICM_TYPER characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about what features the GIC implementation supports.</p>
      <h2>Configuration</h2>
        <p>This register is available in all configurations of the GIC. When <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS==0, this register is Common.</p>
      <h2>Attributes</h2>
        <p>GICM_TYPER is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31">Valid</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_30">CLR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-29_29">SR</a></td><td class="lr" colspan="13"><a href="#fieldset_0-28_16">INTID</a></td><td class="lr" colspan="5"><a href="#fieldset_0-15_11">RES0</a></td><td class="lr" colspan="11"><a href="#fieldset_0-10_0">NumSPIs</a></td></tr></tbody></table><h4 id="fieldset_0-31_31">Valid, bit [31]</h4><div class="field">
      <p>Reports whether GICM_TYPER content is valid.</p>
    <table class="valuetable"><tr><th>Valid</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>GICM_TYPER reports no information on the capabilities of the GICM frame, all other fields are <span class="arm-defined-word">RES0</span>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>GICM_TYPER reports information on capabilities of GICM frame.</p>
        </td></tr></table></div><h4 id="fieldset_0-30_30">CLR, bit [30]</h4><div class="field">
      <p>Reports whether MSI clear registers are supported.</p>
    <table class="valuetable"><tr><th>CLR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>MSI clear registers not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>MSI clear registers implemented.</p>
        </td></tr></table></div><h4 id="fieldset_0-29_29">SR, bit [29]</h4><div class="field">
      <p>Reports whether Secure aliases of MSI registers are supported.</p>
    <table class="valuetable"><tr><th>SR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Secure aliases of MSI registers not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Secure aliases of MSI registers implemented.</p>
        </td></tr></table></div><h4 id="fieldset_0-28_16">INTID, bits [28:16]</h4><div class="field">
      <p>INTID of the first SPI assigned to this GICM frame.</p>
    </div><h4 id="fieldset_0-15_11">Bits [15:11]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-10_0">NumSPIs, bits [10:0]</h4><div class="field">
      <p>Number of SPIs assigned to this GICM frame.</p>
    </div><h2>Accessing GICM_TYPER</h2><h4>GICM_TYPER can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Distributor</td><td>MSI_base</td><td><span class="hexnumber">0x0004</span></td><td>GICM_TYPER</td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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